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The NSLU2 has an Intel IXP420 as its processor. Currently NSLU2's are supplied with a B0 stepping IXP420. This is a stripped down version of the IXP425 and therefore does not have any of the cryptographic features or extra interfaces. The XScale core inside the IXP420 is based on a ARMv5TE architecture and is rated for 266MHz operation. Units supplied by Linksys, before May 2006 run at 133 Mhz and can set for 266MHz operation using a simple modification. After this manufacture date, most users have discovered their Nslu2 already operating at 266MHz. Due to limitations of the IXP NPE access library and microcode at the time of release, the NSLU2 runs in big endian mode (the cpu supports little endian as well).

The CPU is connected to 8MB of flash memory and 32MB of SDRAM on the PCB.

There are two MII interfaces of which only one is wired to an Ethernet PHY. The other MII interface is not accessible at all as the designers of the PCB did not bring the necessary BGA ball connections out.

The IXP420 has two serial ports, one is used for the serial console on J2 and the other is a receive only port as it is partially connected. Please see PinoutOfInternalSerialPort for more details.

The PCI bus is used to connect the NEC USB chip to the IXP420 and it is possible to connect any 33MHz PCI device to it, the required lines are even brought out of the BGA-chip. Since one 33MHZ deivice is enough to slow down every 66MHZ device to 33MHz, removal of the NEC USB chip is only necessary to run a 66MHz PCI bus.

until yet It has not been verified whetever any nslu2 firmware kernel supports irq sharing needed to run more than one pci device on the isp420, nor whetever any firmware's kernel scans the bus for devices and whetever they exclude/disregard recognized devices when mapping pci device addresses to the memory address space.

The expansion bus is used to connect the flash chip. It has not been verified whether the other expansion bus enables have been brought out. The expansion bus is also used for configuration of the XScale core.

The JTAG port is connected to several unpopulated resistor pads on the reverse of the PCB. Please see PinoutOfJTAGPort for more details.

The IXP420 GPIO pins are all used for various functions and are not available.

The IXP420 has some DSP features like a MAC (multiply/accumulate) unit featuring a 40-bit accumulator and support for 16-bit packed data. These can be accessed using a software library from Intel. The library is a "software module that provides the basic voice and signal-processing functionalities for voice-over-Internet-protocols (VoIP) applications..." It provides functions for a-law and μ-law compression/decompression, high pass filters and echo cancellation as explained in the API Reference Manual and the Programmer's Guide.

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Based on work by BrianZhou, xkr47, carrick, tman, Anonymous, A, rwhitby, jkpeters_37, and kolla.
Originally by tman.
Page last modified on December 27, 2009, at 02:44 PM